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FEATURES Complete 16-Bit D/A Function On-Chip Output Amplifier On-Chip Buried Zener Voltage Reference 1 LSB Integral Linearity 15-Bit Monotonic over Temperature Microprocessor Compatible Serial or Byte Input Double Buffered Latches Fast (40 ns) Write Pulse Asynchronous Clear (to 0 V) Function Serial Output Pin Facilitates Daisy Chaining Unipolar or Bipolar Output Low Glitch: 15 nV-s Low THD+N: 0.009% PRODUCT DESCRIPTION
UNI/BIP CLR/ CS LBE 15 HBE 16 SER 17 CLR 18 LDAC 19 10k REF IN 23 CONTROL LOGIC 14
Monolithic 16-Bit Serial/Byte DACPORT AD660
FUNCTIONAL BLOCK DIAGRAM
SIN/ MSB/LSB/ DB7 DB0 DB1 12 11 5
AD660
16-BIT LATCH 10k 16-BIT LATCH 10.05k 16-BIT DAC 21 V OUT +10V REF 20 AGND 24 REF OUT 1 2 3 4 -VEE +VCC +VLL DGND 22 SPAN/ BIP OFFSET 13 S OUT
PRODUCT HIGHLIGHTS
The AD660 DACPORT(R) is a complete 16-bit monolithic D/A converter with an on-board voltage reference, double buffered latches and output amplifier. It is manufactured on Analog Devices' BiMOS II process. This process allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry. The AD660's architecture ensures 15-bit monotonicity over time and temperature. Integral and differential nonlinearity is maintained at 0.003% max. The on-chip output amplifier provides a voltage output settling time of 10 s to within 1/2 LSB for a full-scale step. The AD660 has an extremely flexible digital interface. Data can be loaded into the AD660 in serial mode or as two 8-bit bytes. This is made possible by two digital input pins which have dual functions. The serial mode input format is pin selectable to be MSB or LSB first. The serial output pin allows the user to daisy chain several AD660s by shifting the data through the input latch into the next DAC thus minimizing the number of control lines required to SIN, CS and LDAC. The byte mode input format is also flexible in that the high byte or low byte data can be loaded first. The double buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multi-DAC system. The AD660 is available in five grades. AN and BN versions are specified from -40C to +85C and are packaged in a 24-pin 300 mil plastic DIP. AR and BR versions are also specified from -40C to +85C and are packaged in a 24-pin SOIC. The SQ version is packaged in a 24-pin 300 mil cerdip package and is also available compliant to MIL-STD-883. Refer to the AD660/ 883B data sheet for specifications and test conditions.
DACPORT is a registered trademark of Analog Devices, Inc.
1. The AD660 is a complete 16-bit DAC, with a voltage reference, double buffered latches and output amplifier on a single chip. 2. The internal buried Zener reference is laser trimmed to 10.000 volts with a 0.1% maximum error and a temperature drift performance of 15 ppm/C. The reference is available for external applications. 3. The output range of the AD660 is pin programmable and can be set to provide a unipolar output range of 0 V to +10 V or a bipolar output range of -10 V to +10 V. No external components are required. 4. The AD660 is both dc and ac specified. DC specifications include 1 LSB INL and 1 LSB DNL errors. AC specifications include 0.009% THD+N and 83 dB SNR. 5. The double buffered latches on the AD660 eliminate data skew errors and allow simultaneous updating of DACs in multi-DAC applications. 6. The CLEAR function can asynchronously set the output to 0 V regardless of whether the DAC is in unipolar or bipolar mode. 7. The output amplifier settles within 10 s to 1/2 LSB for a full-scale step and within 2.5 s for a 1 LSB step over temperature. The output glitch is typically 15 nV-s when a fullscale step is loaded.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD660-SPECIFICATIONS
Parameter RESOLUTION DIGITAL INPUTS (TMIN to TMAX) VIH (Logic "1") VIL (Logic "0") IIH (VIH = 5 5 V) IIL (VIL = 0 V) TRANSFER FUNCTION CHARACTERISTICS 1 Integral Nonlinearity TMIN to TMAX Differential Nonlinearity TMIN to TMAX Monotonicity Over Temperature Gain Error2, 3 Gain Drift (TMIN to TMAX) DAC Gain Error4 DAC Gain Drift4 Unipolar Offset Unipolar Offset Drift (T MIN to TMAX) Bipolar Zero Error Bipolar Zero Error Drift (T MIN to TMAX) REFERENCE INPUT Input Resistance Bipolar Offset Input Resistance REFERENCE OUTPUT Voltage Drift External Current5 Capacitive Load Short Circuit Current OUTPUT CHARACTERISTICS Output Voltage Range Unipolar Configuration Bipolar Configuration Output Current Capacitive Load Short Circuit Current POWER SUPPLIES Voltage VCC6 VEE6 VLL Current (No Load) ICC IEE ILL @ VIH, VIL = 5, 0 V @ VIH, VIL = 2.4, 0.4 V Power Supply Sensitivity Power Dissipation (Static, No Load) TEMPERATURE RANGE Specified Performance (A, B) Specified Performance (S)
(TA = +25 C, VCC = +15 V, VEE = -15 V, VLL = +5 V unless otherwise noted)
AD660AN/AR/SQ Min Typ Max 16 2.0 0 5.5 0.8 10 10 2 4 2 4 14 0.10 25 0.05 10 2.5 3 7.5 5 10 10 10.00 4 1000 25 * 13 13 10.01 25 15 * 15 * * * * * * * * * * * * * * * * * * 15 AD660BN/BR Typ Max
Min 16 * *
Units Bits
* * * * 1 2 1 2
Volts Volts A A LSB LSB LSB LSB Bits % of FSR ppm/C % of FSR ppm/C mV ppm/C mV ppm/C k k Volts ppm/C mA pF mA
7 7 9.99 2
0 -10 5 25
+10 +10 1000
* * * *
* * *
Volts Volts mA pF mA
+13.5 -13.5 +4.5 +12 -12 0.3 3 1 365 -40 -55
+16.5 -16.5 +5.5 +18 -18 2 7.5 2 625 +85 +125
* * * * * * * * * *
* * * * * * * * * *
Volts Volts Volts mA mA mA mA ppm/% mW C C
NOTES 1 For 16-bit resolution, 1 LSB = 0.0015% of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR. For 14-bit resolution, 1 LSB = 0.006% of FSR. FSR stands for Full-Scale Range and is 10 V in a Unipolar Mode and 20 V in Bipolar Mode. 2 Gain error and gain drift are measured using the internal reference. The internal reference is the main contributor to gain drift. If lower gain drift is required, the AD660 can be used with a precision external reference such as the AD587, AD586 or AD688. 3 Gain Error is measured with fixed 50 resistors as shown in the Application section. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar mode) or 0.50% of FSR (Bipolar mode). 4 DAC Gain Error and Drift are measured with an external voltage reference. They represent the error contributed by the DAC alone, for use with an external reference. 5 External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD660. 6 Operation on 12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference section. *Indicates that the specification is the same as AD660AN/AR/SQ. Specifications subject to change without notice.
-2-
REV. A
AD660 AC PERFORMANCE CHARACTERISTICS
Parameter Output Settling Time (Time to 0.0008% FS with 2 k, 1000 pF Load) Limit 13 8 10 6 8 2.5 0.009 0.056 5.6 83 15 2 120 125
(With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. TMIN TA TMAX, VCC = +15 V, VEE = -15 V, VLL = +5 V except where noted.)
Units s max s typ s typ s typ s typ s typ % max % max % max dB min nV-s typ nV-s typ nV/Hz typ nV/Hz typ Test Conditions/Comments 20 V Step, TA = +25C 20 V Step, TA = +25C 20 V Step, TMIN TA TMAX 10 V Step, TA = +25C 10 V Step, TMIN TA TMAX 1 LSB Step, TMIN TA TMAX 0 dB, 990.5 Hz; Sample Rate = 96 kHz; TA = +25C -20 dB, 990.5 Hz; Sample Rate = 96 kHz; TA = +25C -60 dB, 990.5 Hz; Sample Rate = 96 kHz; TA = +25C TA = +25C DAC Alternately Loaded with 8000H and 7FFFH DAC Alternately Loaded with 0000H and FFFFH; CS High Measured at VOUT; 20 V Span; Excludes Reference Measured at REF OUT
Total Harmonic Distortion + Noise A, B, S Grade A, B, S Grade A, B, S Grade Signal-to-Noise Ratio Digital-to-Analog Glitch Impulse Digital Feedthrough Output Noise Voltage Density (1 kHz - 1 MHz) Reference Noise
Specifications subject to change without notice.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD660 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS*
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
-V +V
EE
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +17.0 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -17.0 V VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V Digital Inputs (Pins 5 through 23) to DGND . . . . . . -1.0 V to +7.0 V REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 V Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . . 10.5 V Ref Out, VOUT . . . . . . . Indefinite Short to AGND, DGND, VCC, VEE, and VLL Power Dissipation (Any Package) To +60C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW Derates above +60C . . . . . . . . . . . . . . . . . . . . 8.7 mW/C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1 2 3 4 5 6 7 8
24 REF OUT 23 REF IN 22 SPAN, BIPOLAR OFFSET 21 VOUT 20 AGND
CC LL
+V
DGND DB7, 15 DB6, 14 DB5, 13 DB4, 12
AD660
TOP VIEW (Not to Scale)
19 18
LDAC CLR
17 SER 16 15 14 13 HBE LBE, UNI/BIP CLEAR CS S
OUT
DB3, 11 9 DB2, 10 10
DB1, 9, MSB/LSB 11 DB0, 8, SIN 12
REV. A
-3-
AD660
ORDERING GUIDE
Model AD660AN AD660AR AD660BN AD660BR AD660SQ AD660SQ/883B**
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C
Linearity Error Max +25C 2 LSB 2 LSB 1 LSB 1 LSB 2 LSB 2 LSB
Linearity Error Max Gain TC max Package Package TMIN - TMAX ppm/C Description Option* 4 LSB 4 LSB 2 LSB 2 LSB 4 LSB ** 25 25 15 15 25 ** Plastic DIP SOIC Plastic DIP SOIC Cerdip ** N-24 R-24 N-24 R-24 Q-24 **
*N = Plastic DIP; Q = Cerdip; R = SOIC. **Refer to AD660/883B military data sheet.
TIMING CHARACTERISTICS V
Parameter (Figure la) tCS tDS tDH tBES tBEH tLH tLW (Figure lb) tCLK tLO tHI tSS tDS tDH tSH tLH tLW (Figure lc) tCLR tSET tHOLD (Figure ld) tPROP tDS 40 40 0 40 0 80 40 80 30 30 0 40 0 0 80 40 80 80 0 50 50
CC
= +15 V, VEE = -15 V, VLL = +5 V, VHI = 2.4 V, VLO = 0.4 V
Limit -55C to +125C 50 50 10 50 10 100 50 100 50 50 10 50 10 10 100 50 110 110 10 100 80 Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Limit +25C
Specifications subject to change without notice.
BIT 0-7
tDS
HBE OR LBE
tDH
tBES tCS
CS
tBEH
tLH
LDAC
tLW
Figure 1a. AD660 Byte Load Timing
-4-
REV. A
AD660
BIT0 VALID 1 VALID 16
tDS
SER
tDH
tSH
tSS
BIT1
"1" = MSB FIRST, "0" = LSB FIRST
tLO
CS
tHI
tCLK
LDAC
tLH
tLW
Figure 1b. AD660 Serial Load Timing
tCLR
CLR
tSET
LBE "1" = BIP 0, "0" = UNI 0
tHOLD
Figure 1c. Asynchronous Clear to Bipolar or Unipolar Zero
BIT0 VALID 16 VALID 17
tDS
SER BIT 1 (MSB/LSB) CS
tPROP
SERIAL OUT VALID SOUT1
Figure 1d. Serial Out Timing
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY: Analog Devices defines integral nonlinearity as the maximum deviation of the actual, adjusted DAC output from the ideal analog output (a straight line drawn from 0 to FS-1 LSB) for any bit combination. This is also referred to as relative accuracy. DIFFERENTIAL NONLINEARITY: Differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with a 1 LSB change in the digital input code. Monotonic behavior requires that the differential linearity error be greater than or equal to -1 LSB over the temperature range of interest. MONOTONICITY: A DAC is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output will always be a single-valued function of the input. GAIN ERROR: Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. OFFSET ERROR: Offset error is a combination of the offset errors of the voltage-mode DAC and the output amplifier and is measured with all 0s loaded in the DAC. REV. A
BIPOLAR ZERO ERROR: When the AD660 is connected for bipolar output and 10 . . . 000 is loaded in the DAC, the deviation of the analog output from the ideal midscale value of 0 V is called the bipolar zero error. DRIFT: Drift is the change in a parameter (such as gain, offset and bipolar zero) over a specified temperature range. The drift temperature coefficient, specified in ppm/C, is calculated by measuring the parameter at TMIN, 25C and TMAX and dividing the change in the parameter by the corresponding temperature change. TOTAL HARMONIC DISTORTION + NOISE: Total harmonic distortion + noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent (%). THD+N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and noise. The distribution of these errors may be different, depending upon the amplitude of the output signal. Therefore, to be the most useful, THD+N should be specified for both large and small signal amplitudes.
-5-
AD660
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is defined as the ratio of the amplitude of the output when a fullscale signal is present to the output with no signal present. This is measured in dB. DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is measured at half scale when the DAC switches around the MSB and as many as possible switches change state, i.e., from 011 . . . 111 to 100 . . . 000. DIGITAL FEEDTHROUGH: When the DAC is not selected (i.e., CS is held high), high frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the VOUT pin. This noise is digital feedthrough.
THEORY OF OPERATION
(Pin 21), and between REF OUT (Pin 24) and REF IN (Pin 23). It is possible to use the AD660 without any external components by tying Pin 24 directly to Pin 23 and Pin 22 directly to Pin 21. Eliminating these resistors will increase the gain error by 0.25% of FSR.
UNI/BIP CLR/ CS LBE 15 HBE 16 SER 17 CLR 18 LDAC 19 10k 23 REF IN +10V REF 20 AGND R1 50 24 REF OUT 1 2 3 +VLL DGND 4 -VEE +VCC 16-BIT DAC 21 VOUT OUTPUT CONTROL LOGIC 16-BIT LATCH 10.05k 14 SIN/ MSB/LSB/ DB0 DB1 DB7 12 11 5
AD660
16-BIT LATCH 10k 22 13 SOUT SPAN/ BIP OFF R2 50
The AD660 uses an array of bipolar current sources with MOS current steering switches to develop a current proportional to the applied digital word, ranging from 0 to 2 mA. A segmented architecture is used, where the most significant four data bits are thermometer decoded to drive 15 equal current sources. The lesser bits are scaled using a R-2R ladder, then applied together with the segmented sources to the summing node of the output amplifier. The internal span/bipolar offset resistor can be connected to the DAC output to provide a 0 V to +10 V span, or it can be connected to the reference input to provide a -10 V to +10 V span.
UNI/BIP CLR/ CS LBE 15 HBE 16 SER 17 CLR 18 LDAC 19 10k REF IN 23 16-BIT DAC 21 V OUT +10V REF 20 AGND 24 REF OUT 1 2 3 4 CONTROL LOGIC 16-BIT LATCH 10.05k 14 SIN/ MSB/LSB/ DB7 DB0 DB1 12 11 5
Figure 3a. 0 V to +10 V Unipolar Voltage Output
If it is desired to adjust the gain and offset errors to zero, this can be accomplished using the circuit shown in Figure 3b. The adjustment procedure is as follows: STEP 1 . . . ZERO ADJUST Turn all bits OFF and adjust zero trimmer, R4, until the output reads 0.000000 volts (1 LSB = 153 V). STEP 2 . . . GAIN ADJUST Turn all bits ON and adjust gain trimmer, R1, until the output is 9.999847 volts. (Full scale is adjusted to 1 LSB less than the nominal full scale of 10.000000 volts).
UNI/BIP CLR/ LBE CS 15 HBE 16 SER 17 CLR 18 LDAC 19 REF IN 10k 23 16-BIT DAC 21 OUTPUT +10V REF 20 24 REF OUT R1 100 1 -V
EE
AD660
16-BIT LATCH 10k 22 SPAN/ BIP OFFSET 13 S OUT
SIN/ MSB/LSB/ DB0 DB1 DB7 12 11 5
14
AD660
16-BIT LATCH CONTROL LOGIC 16-BIT LATCH 13 S SPAN/ 10k BIP OFF 22 10.05k
OUT
+VCC
R3 16k
R4 10k
R2 50
-V
EE
-VEE +VCC
+VLL DGND
Figure 2. AD660 Functional Block Diagram
ANALOG CIRCUIT CONNECTIONS
2 +V
CC
Internal scaling resistors provided in the AD660 may be connected to produce a unipolar output range of 0 V to +10 V or a bipolar output range of -10 V to +10 V. Gain and offset drift are minimized in the AD660 because of the thermal tracking of the scaling resistors with other device components.
UNIPOLAR CONFIGURATION
3 +V
LL
4
DGND
AGND
Figure 3b. 0 V to +10 V Unipolar Voltage Output with Gain and Offset Adjustment
The configuration shown in Figure 3a will provide a unipolar 0 V to +10 V output range. In this mode, 50 resistors are tied between the span/bipolar offset terminal (Pin 22) and VOUT
-6-
REV. A
AD660
BIPOLAR CONFIGURATION
The circuit shown in Figure 4a will provide a bipolar output voltage from -10.000000 V to +9.999694 V with positive full scale occurring with all bits ON. As in the unipolar mode, resistors R1 and R2 may be eliminated altogether to provide AD660 bipolar operation without any external components. Eliminating these resistors will increase the gain error by 0.50% of FSR in the bipolar mode.
R2 50 UNI/BIP CLR/ LBE CS 15 HBE 16 SER 17 CLR 18 LDAC 19 10k R1 50 23 REF IN +10V REF 20 24 REF OUT 1 2 3 +VLL DGND AGND 4 -VEE +VCC 16-BIT DAC 21 CONTROL LOGIC 16-BIT LATCH 10.05k VOUT OUTPUT 14 SIN/ MSB/LSB/ DB0 DB1 DB7 12 11 5
It should be noted that using external resistors will introduce a small temperature drift component beyond that inherent in the AD660. The internal resistors are trimmed to ratio-match and temperature-track other resistors on chip, even though their absolute tolerances are 20% and absolute temperature coefficients are approximately -50 ppm/C . In the case that external resistors are used, the temperature coefficient mismatch between internal and external resistors, multiplied by the sensitivity of the circuit to variations in the external resistor value, will be the resultant additional temperature drift.
INTERNAL/EXTERNAL REFERENCE USE
AD660
16-BIT LATCH 10k 22 SPAN/ BIP OFF 13 SOUT
The AD660 has an internal low noise buried Zener diode reference which is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for use in a high speed DAC and will give long-term stability equal or superior to the best discrete Zener diode references. The performance of the AD660 is specified with the internal reference driving the DAC and with the DAC alone (for use with a precision external reference ). The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the DAC (typically 1 mA to REF IN and 1 mA to BIPOLAR OFFSET). A minimum of 2 mA is available for driving external loads. The AD660 reference output should be buffered with an external op amp if it is required to supply more than 4 mA total current. The reference is tested and guaranteed to 0.2% max error. It is also possible to use external references other than 10 volts with slightly degraded linearity specifications. The recommended range of reference voltages is +5 V to +10.24 V, which allows 5 V, 8.192 V and 10.24 V ranges to be used. For example, by using the AD586 5 V reference, outputs of 0 V to +5 V unipolar or 5 V bipolar can be realized. Using the AD586 voltage reference makes it possible to operate the AD660 with 12 V supplies with 10% tolerances.
Figure 4a. 10 V Bipolar Voltage Output
Gain offset and bipolar zero errors can be adjusted to zero using the circuit shown in Figure 4b as follows: STEP I . . . OFFSET ADJUST Turn OFF all bits. Adjust trimmer R2 to give 10.000000 volts output. STEP II . . . GAIN ADJUST Turn all bits ON and adjust R1 to give a reading of +9.999694 volts. STEP III . . . BIPOLAR ZERO ADJUST (Optional) In applications where an accurate zero output is required, set the MSB ON, all other bits OFF, and readjust R2 for zero volts output.
R2 100 UNI/BIP CLR/ CS LBE 15 HBE 16 SER 17 CLR 18 19 23 R1 100 REF IN +10V REF 20 24 REF OUT 1 2 3 +VLL DGND 4 AGND -VEE +VCC LDAC 10.05k 10k 16-BIT DAC 21 VOUT OUTPUT CONTROL LOGIC 16-BIT LATCH 14 SIN/ MSB/LSB/ DB0 DB1 DB7 12 11 5
AD660
16-BIT LATCH 10k 22 SPAN/ BIP OFF 13 SOUT
Figure 4b. 10 V Bipolar Voltage Output with Gain and Offset Adjustment
REV. A
-7-
AD660
Figure 5 shows the AD660 using the AD586 precision 5 V reference in the bipolar configuration. The highest grade AD586MN is specified with a drift of 2 ppm/C which is a 7.5x improvement over the AD660's internal reference. This circuit includes two optional potentiometers and one optional resistor that can be used to adjust the gain, offset and bipolar zero errors in a manner similar to that described in the BIPOLAR CONFIGURATION section. Use -5.000000 V and +4.999847 as the output values. The AD660 can also be used with the AD587 10 V reference, using the same configuration shown in Figure 5 to produce a 10 V output. The highest grade AD587LR, N is specified at 5 ppm/C, which is a 3x improvement over the AD660's internal reference. Figure 6 shows the AD660 using the AD680 precision 10 V reference, in the unipolar configuration. The highest grade AD688BQ is specified with a temperature coefficient of 1.5 ppm/C. The 10 V output is also ideal for providing precise biasing for the offset trim resistor R4.
R2 50 UNI/BIP CLR/ CS LBE 15 HBE 16 SER 17 2 +VCC VOUT 6 CLR 18 LDAC 19 10k 23 R1 100 R2 10k REF IN +10V REF 20 AGND TRIM 5 GND 4 24 REF OUT 1 2 3 +VLL DGND 4 -VEE +VCC 16-BIT DAC 21 VOUT OUTPUT CONTROL LOGIC 16-BIT LATCH 10.05k 14 SIN/ MSB/LSB/ DB0 DB1 DB7 12 11 5
AD660
16-BIT LATCH 10k 22 SPAN/ BIP OFF 13 SOUT
AD586
Figure 5. Using the AD660 with the AD586 5 V Reference
UNI/BIP CLR/ LBE CS 15 HBE 16 SER 17 CLR 18 LDAC 19 10k 23 7 6 4 3 A3 RS A1 R4 R2 R1 R5 A4 R6 15 2 +VCC 16 -VEE 5 9 10 8 12 11 13 1 R1 100 REF IN CONTROL LOGIC 14
SIN/ MSB/LSB/ DB0 DB1 DB7 12 11 5
AD660
16-BIT LATCH 13 SOUT SPAN/ 10k BIP OFF 22 R3 10k R4 10k
16-BIT LATCH
10.05k 16-BIT DAC 21 +10V REF 24 REF OUT 1 2 3 +VLL DGND 4 VOUT
R2 100 OUTPUT 0 TO +10V
20 AGND -VEE +VCC
AD688
14
R3
A2
Figure 6. Using the AD660 with the AD688 High Precision 10 V Reference
-8-
REV. A
AD660
OUTPUT SETTLING AND GLITCH DIGITAL CIRCUIT DETAILS
The AD660's output buffer amplifier typically settles to within 0.0008% FS (1/2 LSB) of its final value in 8 s for a full-scale step. Figures 7a and 7b show settling for a full-scale and an LSB step, respectively, with a 2 k, 1000 pF load applied. The guaranteed maximum settling time at +25C for a full-scale step is 13 s with this load. The typical settling time for a 1 LSB step is 2.5 s. The digital-to-analog glitch impulse is specified as 15 nV-s typical. Figure 7c shows the typical glitch impulse characteristic at the code 011 . . . 111 to 100 . . . 000 transition when loading the second rank register from the first rank register.
600 +10
VOLTS
The AD660 has several "dual-use" pins which allow flexible operation while maintaining the lowest possible pin count and consequently the smallest package size. The user should, therefore, pay careful attention to the following information when applying the AD660. Data can be loaded into the AD660 in serial or byte mode as described below. Serial Mode Operation is enabled by bringing SER (Pin 17) low. This changes the function of DB0 (Pin 12) to that of the serial input pin, SIN. It also changes the function of DB1 (Pin 11) to a control input that tells the AD660 whether the serial data is going to be loaded MSB or LSB first. In serial mode HBE and LBE are effectively disabled except for LBE's dual function which is to control whether the user wishes to have the asynchronous clear function go to unipolar or bipolar zero. (A low on LBE, when CLR is strobed, sends the DAC output to unipolar zero, a high to bipolar zero.) The AD660 does not care about the status of HBE when in serial mode. Data is clocked into the input register on the rising edge of CS as shown in Figure 1b. The data is then resident in the first rank latch and can be loaded into the DAC latch by taking LDAC high. This will cause the DAC to change to the appropriate output value. It should be noted that the clear function clears the DAC latch but does not clear the first rank latch. Therefore, the data that was previously resident in the first rank latch can be reloaded simply by bringing LDAC high after the event that necessitated CLR to be strobed has ended. Alternatively, new data can be loaded into the first rank latch if desired. The serial out pin (SOUT) can be used to daisy chain several DACs together in multi-DAC applications to minimize the number of isolators being used to cross an intrinsic safety barrier. The first rank latch simply acts like a 16-bit shift register, and repeated strobing of CS will shift the data out through SOUT and into the next DAC. Each DAC in the chain will require its own LDAC signal unless all of the DACs are to be updated simultaneously. Byte Mode Operation is enabled simply by keeping SER high, which configures DB0-DB7 as data inputs. In this mode HBE and LBE are used to identify the data as either the high byte or low byte of the 16-bit input word. (The user can load the data, in any order, into the first rank latch.) As in the serial mode case, the status of LBE, when CLR is strobed determines whether the AD660 clears to unipolar or bipolar zero. Therefore, when in byte mode, the user must take care to set LBE to the desired status before strobing CLR. (In serial mode the user can simply hardware LBE to the desired state.)
400 200
0
0 -200
-10
-400 -600 10 s 20
0
a. -10 V to +10 V Full-Scale Step Settling
600 400 200
V
0
-200 -400 -600 0 2 3 4 5
1
s
b. LSB Step Settling
+10
mV
0
-10
V
0
1
2
s
3
4
5
NOTE: CS is edge triggered. HBE, LBE and LDAC are level triggered.
c. D-to-A Glitch Impulse Figure 7. Output Characteristics
REV. A
-9-
AD660-Microprocessor Interface Section
AD660 TO MC68HC11 (SPI BUS) INTERFACE
The AD660 interface to the Motorola SPI (serial peripheral interface) is shown in Figure 8. The MOSI, SCK, and SS pins of the HC11 are respectively connected to the BIT0, CS and LDAC pins of the AD660. The SER pin of the AD660 is tied low causing the first rank latch to be transparent. The majority of the interfacing issues are taken care of in the software initialization. A typical routine such as the one shown below begins by initializing the state of the various SPI data and control registers. The most significant data byte (MSBY) is then retrieved from memory and processed by the SENDAT subroutine. The SS pin is driven low by indexing into the PORTD data register and clear Bit 5. This causes the 2nd rank latch of the AD660 to become transparent. The MSBY is then set to the SPI data register where it is automatically transferred to the AD660. The HC11 generates the requisite 8 clock pulses with data valid on the rising edges. After the most significant byte is transmitted, the least significant byte (LSBY) is loaded from memory and transmitted in a similar fashion. To complete the transfer, the LDAC pin is driven high latching the complete 16-bit word into the AD660.
INIT LDAA STAA LDAA STAA LDAA STAA LDAA BSR JMP LDY BCLR STAA LDAA BPL LDAA STAA LDAA BPL BSET RTS #$2F PORTD #$38 DDRD #$50 SPCR MSBY SENDAT NEXTPT #$1000 $08,Y,$20 SPDR SPSR WAIT1 LSBY SPDR SPSR WAIT2 $08,Y,$20 ;SS = I; SCK = 0; MOSI = I ;SEND TO SPI OUTPUTS ;SS, SCK,MOSI = OUTPUTS ;SEND DATA DIRECTION INFO ;DABL INTRPTS,SPI IS MASTER & ON ;CPOL=0, CPHA = 0,1MHZ BAUD RATE ;LOAD ACCUM W/UPPER 8 BITS ;JUMP TO DAC OUTPUT ROUTINE ;INFINITE LOOP ;POINT AT ON-CHIP REGISTERS ;DRIVE SS (LDAC) LOW ;SEND MS-BYTE TO SPI DATA REG ;CHECK STATUS OF SPIE ;POLL FOR END OF X-MISSION ;GET LOW 8 BITS FROM MEMORY ;SEND LS-BYTE TO SPI DATA REG ;CHECK STATUS OF SPIE ;POLL FOR END OF X-MISSION ;DRIV SS HIGH TO LATCH DATA
MICROWIRETM SO SK G1
BIT0 CS LDAC SER
AD660
Figure 9. AD660 to MICROWIRE Interface
AD660 TO ADSP-210x FAMILY INTERFACE
The serial mode of the AD660 minimizes the number of control and data lines required to interface to digital signal processors (DSPs) such as the ADSP-210x family. The application in Figure 10 shows the interface between an ADSP-2101 and the AD660. Both the TFS pin and the DT pins of the ADSP-2101 should be connected to the SER and BIT0 pins of the AD660, respectively. An inverter is required between the SCLK output and the CS input of the AD660 in order to assure that data transmitted to the BIT0 pin is valid on the rising edge of CS. The serial port (SPORT) of the DSP should be configured for alternate framing mode so that TFS complies with the wordlength framing requirement of SER. Note that the INVTFS bit in the SPORT control register should be set to invert the TFS signal so that SER is the correct polarity. The LDAC signal, which must meet the minimum hold specification of tIH, is easily generated by delaying the rising edge of SER with a 74HC74 flip-flop. The CS signal clocks the flip-flop resulting in a delay of approximately one CS clock cycle. In applications such as waveform generation, accurate timing of the output samples is important to avoid noise that would be induced by jitter on the LDAC signal. In this example, the ADSP-2101 is set up to use the internal timer to interrupt the processor at the precise and desired sample rate. When the timer interrupt occurs, the processors's 16-bit data word is written to the transmit register (TXn). This causes the DSP to automatically generate the TFS signal and begin transmission of the data.
ADSP-210x SCLK 74HC04 CS BIT0
NEXTPT
SENDAT
WAIT1
WAIT2
68HC11 MDSI SCK SS BIT0 CS LDAC SER
DT
AD660
AD660
TFS D Q 74HC74 LDAC SER
Figure 8. AD660 to 68HC11 (SPI) Interface
AD660 TO MICROWIRE INTERFACE
Figure 10. AD660 to ADSP-210x Interface
AD660 TO Z80 INTERFACE
The flexible serial interface of the AD660 is also compatible with the National Semiconductor MICROWIRETM interface. The MICROWIRE interface is used on microcontrollers such as the COP400 and COP800 series of processors. A generic interface to the MICROWIRE interface is shown in Figure 9. The G1, SK, And SO pins of the MICROWIRE interface are respectively connected to the LDAC, CS and BIT0 pins of the AD660.
MICROWIRE is a registered trademark of National Semiconductor.
Figure 11 shows a Zilog Z-80 8-bit microprocessor connected to the AD660 using the byte mode interface. The double-buffered capability of the AD660 allows the microprocessor to independently write to the low and high byte registers, and update the DAC output. Processor speeds up to 6 MHz on Z-80B require no extra wait states to interface with the AD660 using a 74ALS138 as the address decoder.
-10-
REV. A
Applications Information-AD660
The address decoder analyzes the input-output address produced by the processor to select the function to be performed by the AD660, qualified by the coincidence of the Input-Output Request (IORQ*) and Write (WR*) pins. The least significant address bit (A0) determines if the low or high byte register of the AD660 is active. More significant address bits select between input register loading, DAC output update, and unipolar or bipolar clear. A typical Z-80 software routine begins by writing the low byte of the desired 16-bit DAC data to address 0, followed by the high byte to address 1. The DAC output is then updated by activating LDAC with a write to address 2 (or 3). A clear to unipolar zero occurs on a write to address 4, and a clear to bipolar zero is performed by a write to address 5. The actual data written to addresses 2 through 5 is irrelevant. The decoder can easily be expanded to control as many AD660s as required.
D0-D7 +5V
1000
NOISE VOLTAGE - nV/
Hz
100 10 1 1
10
100
1k
10k
100k
1M
10M
FREQUENCY - Hz
Figure 13. Reference Noise Voltage Spectral Density
BOARD LAYOUT
ADDRESS DECODE Y2 IORQ WR E2 Y1 E1 Y0 A1-A15 A0 A0-A15
DB0-DB7 SER CLR LDAC CS
V
LL
AD660
Designing with high resolution data converters requires careful attention to board layout. Trace impedance is the first issue. A 306 A current through a 0.5 trace will develop a voltage drop of 153 V, which is 1 LSB at the 16-bit level for a 10 V full-scale span. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to filter out ac noise. Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog and digital ground planes should also be used, with a single interconnection point to minimize ground loops. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. One feature that the AD660 incorporates to help the user layout is that the analog pins (VCC, VEE, REF OUT, REF IN, SPAN/ BIP OFFSET, VOUT and AGND) are adjacent to help isolate analog signals from digital signals.
SUPPLY DECOUPLING
Z80
HBE LBE DGND
Figure 11. Connections for 8-Bit Bus Interface
NOISE
In high resolution systems, noise is often the limiting factor. A 16-bit DAC with a 10 volt span has an LSB size of 153 V (-96 dB). Therefore, the noise floor must remain below this level in the frequency range of interest. The AD660's noise spectral density is shown in Figures 12 and 13. Figure 12 shows the DAC output noise voltage spectral density for a 20 V span excluding the reference. This figure shows the 1/f corner frequency at 100 Hz and the wideband noise to be below 120 nV/Hz. Figure 13 shows the reference noise voltage spectral density. This figure shows the reference wideband noise to be below 125 nV/Hz.
1000
Hz
The AD660 power supplies should be well filtered, well regulated, and free from high frequency noise. Switching power supplies are not recommended due to their tendency to generate spikes which can induce noise in the analog system. Decoupling capacitors should be used in very close layout proximity between all power supply pins and ground. A 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor provides adequate decoupling. VCC and VEE should be bypassed to analog ground, while VLL should be decoupled to digital ground. An effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD660, associated analog circuitry and interconnections as far as possible from logic circuitry. A solid analog ground plane around the AD660 will isolate large switching ground currents. For these reasons, the use of wire wrap circuit construction is not recommended; careful printed circuit construction is preferred. -11-
NOISE VOLTAGE - nV/
100
10
1
1
10
100
1k
10k
100k
1M
10M
FREQUENCY - Hz
Figure 12. DAC Output Noise Voltage Spectral Density
REV. A
AD660
GROUNDING
If a single AD660 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
N-24 24-Lead Plastic DIP
2 4 1 13 0.280 (7.11) 0.240 (6.10) 12
PIN 1
1.275 (32.30) 1.125 (28.60) 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204)
Q-24 24-Lead Cerdip
0.005 (0.13) MIN 0.098 (2.49) MAX
PIN 1
2 4 1 1.060 (26.92) MAX
1 3 12
0.310 (7.87) 0.220 (5.59) 0.320 (8.13) 0.290 (7.37)
0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76)
0.060 (1.52) 0.015 (0.38)
0.150 (3.81) MIN SEATING PLANE
0.015 (0.38) 0.008 (0.20) 15 0
R-24 24-Lead Small Outline (SOIC)
PRINTED IN U.S.A.
0.0500 (1.27) 0.0157 (0.40)
24
13 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00)
PIN 1 1 12
0.6141 (15.60) 0.5985 (15.20)
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25) x 45
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0125 (0.32) 0.0091 (0.23)
8 0
-12-
REV. A
C1813a-15-7/93
The AD660 has two pins, designated analog ground (AGND) and digital ground (DGND.) The analog ground pin is the "high quality" ground reference point for the device. Any external loads on the output of the AD660 should be returned to analog ground. If an external reference is used, this should also be returned to the analog ground.
the digital ground plane to DGND keeping lead lengths as short as possible. Then connect AGND and DGND together at the AD660. If multiple AD660s are used or the AD660 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. This single interconnection of grounds prevents large ground loops and consequently prevents digital currents from flowing through the analog ground.

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